1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device and a semiconductor device manufactured by the method, and more particularly, to a method of manufacturing a semiconductor device including a MOS transistor, as well as to the structure of a gate electrode of the semiconductor device.
2. Background Art
As the channel length of a MOS transistor is decreased, the aspect ratio of a gate electrode is increased. To solve such a problem of an increase in the aspect ratio, there is a demand for a further reduction in the thickness of a thin film of electrode material. In contrast, there is a typical demand for the gate electrode possessing the masking properties (i.e., blocking properties) with respect to ionizing radiation with a view to maintaining fixed impurity concentrations of a channel region, imposing limitation on the reduction in the film thickness.
FIGS. 14 through 16 are perspective views for explaining an existing method of manufacturing a semiconductor device.
FIG. 14 shows the structure of a semiconductor device comprising a semiconductor substrate 1 having a gate insulating film 2 formed thereon and a gate electrode 3 formed on the gate insulating film 2. The electrode shown in the drawing is formed from commonly-used polysilicon (Poly-Si) doped with phosphorous. In the case of a MOS transistor having an LDD layer, patterning of the gate electrode 3 is followed by ion-implantation of an impurity layer into the semiconductor substrate 1, thereby forming an LDD layer 5.
FIG. 15 shows a gate electrode 3 immediately after a film 6 used for forming side walls has been deposited on the gate electrode 3. In this case, the film 6 has a two-layer structure comprising a TEOS film 7 and a SiN film 8. The polysilicon included in the gate electrode 3 is increased immensely in grain size through heat treatment during the manufacturing process, and impurity deposition layers C are formed along grain boundaries B. In the case of a polysilicon electrode doped with a particularly high concentration of impurities, there is a noticeable tendency to form impurity deposition layers.
FIG. 16 shows the semiconductor substrate after side walls 9 have been formed. Since the impurity deposition layers C are etched away faster than a silicon monocrystal, the exposed portions of the impurity deposition layers C in the upper surface of the gate electrode 3 are slightly taken away along the grain boundaries B when the film 6 is anisotropically etched away. Such erosion of the impurity deposition layers will be hereinafter referred to as a xe2x80x9clocal-removal phenomenon.xe2x80x9d
FIG. 17 shows a transistor, wherein a source/drain region (S/D) 10 is formed by ion-implantation of impurities into the semiconductor substrate 1 while the gate electrode 3 and the side walls 9 are used as masks. The exposed impurity deposition layers in the gate electrode 3 change to material which is liable to cause a channeling phenomenon at the time of ionizing radiation. Since such a deposition layer exists in the gate electrode 3 in the heightwise direction thereof, the masking properties of the gate electrode 3 are locally deteriorated. Such a phenomenon will be hereinafter referred to as a xe2x80x9cchanneling phenomenon.xe2x80x9d Further, locally-removed areas are more liable to cause the channeling phenomenon.
The influence of local removal or channeling phenomenon mentioned previously on the characteristics of the semiconductor device accounts for a deterioration in the reliability of the gate insulating film. One of the variations in the characteristics of a short-channel transistor is an increase in an off-leakage current. In this phenomenon, the concentration of the channel region is partially changed as a result of channeling of impurities along impurity deposition layers, thereby resulting in an increase in a source/drain leakage current flowing through the areas of the channel region whose concentrations are changed.
In the short-channel transistor, since a gate length approximates to a grain size, the chance of the grain boundaries extending so as to cross the gate electrode in the direction of the channel increases to a much greater extent. Accordingly, there arises a high probability of a transistor being channeled in such a direction as to cross the channel.
A heat treatment process performed during the course of the manufacturing process will now be described in consideration of the geometry of an electrode. At the time of heat treatment following patterning of a gate electrode, heat travels to the inside the gate electrode from its exposed portions (i.e., the upper surface and side walls of the electrode). For this reason, the impurity deposition layers are formed so as to have a larger thickness in the vicinity of the upper surface and side walls of the gate electrode. In a short-channel transistor whose gate length is equivalent to or smaller than the grain size of polysilicon, a local channeling phenomenon is very likely to occur.
In a large-scale integrated circuit comprising defective transistors such as those mentioned previously, a minute leakage current accounts for an increase in a standby current, which in turns hinders a reduction in the power consumption of the semiconductor device.
Direct channeling of impurities into the gate insulating film results in a deterioration in the characteristic of the insulating film or in acceleration of generation of boundary level, which in turn causes a deterioration in the reliability of the gate insulating film or of hot carriers of the transistor.
The present invention has been conceived to solve the aforementioned problems in the background art, and the object of the present invention is to provide a method of manufacturing a semiconductor device, particularly a MOS semiconductor device, whose gate electrode has a structure resistant to a channeling phenomenon at the time of ion implantation so as to lessen the degree of increase in the aspect ratio of the gate electrode which hinders the miniaturization of a semiconductor device, as well as to a semiconductor device manufactured by the method.
Another object of the present invention is to provide a semiconductor device, in which a local channeling phenomenon is prevented from occurring in a gate electrode to thereby achieve a reduction in variations in an off-leakage current, highly accurate controlling of a threshold value, and improved reliability of a gate insulating film.
According to one aspect of the present invention, in a method of manufacturing a semiconductor device, a gate insulating film is formed on a semiconductor substrate. A gate electrode is formed by deposition of semiconductor material on the gate insulating film. An amorphous layer is formed in the gate electrode. Side walls are formed on the gate electrode. Further, impurities are implanted into the semiconductor substrate by ion implantation while the gate electrode and the side walls are used as masks.
In another aspect of the present invention, in the method of manufacturing a semiconductor device, the amorphous layer is formed at least either along the top surface of, along the side surfaces of, or inside the gate electrode.
According to another aspect of the present invention, in a method of manufacturing a semiconductor device, a gate insulating film is formed on a semiconductor substrate. A gate electrode is formed so as to comprise a plurality of separated layers by deposition of semiconductor material on the gate insulating film. Side walls are formed on the gate electrode. Further, impurities are implanted into the semiconductor substrate by ion implantation while the gate electrode and the side walls are used as masks.
According to another aspect of the present invention, in a method of manufacturing a semiconductor device, gate insulating films are formed in respective regions on a semiconductor substrate having different conductivity types. Gate electrodes are formed by deposition of semiconductor material on each of the gate insulating films. Each of nitrogen-containing layers, which are different in nitrogen concentration from each other, is formed along the surface of and/or inside each of the gate electrodes so as to correspond to the conductivity types of the regions of the semiconductor substrate. Side walls are formed on each of the gate electrodes. Further, impurities are implanted into the semiconductor substrate while the gate electrodes and the side walls are used as masks.
According to still another aspect of the present invention, a semiconductor device comprises a semiconductor substrate and a gate insulating film formed on the semiconductor substrate.
A gate electrode is provided in which an amorphous layer having a grain size of 0.05 xcexcm or less is formed along the surface of or inside the gate electrode and/or along the side surfaces of the gate electrode. Further, a conductive region is provided which is formed in the semiconductor substrate by ion implantation after formation of the amorphous layer.